Various electronic devices, particularly those used for radio frequency (RF) wireless communications, typically include amplifiers for amplifying input signals at one or more stages. Some amplifiers, such as Doherty amplifiers, include one or more low quiescent current amplifiers that must be biased to very low currents, such as Class-B mode or Class-C mode amplifiers, as well as amplifiers that must be biased to relatively high currents, such as Class-A mode or Class-AB mode amplifiers. However, conventional bias circuits may become unstable when providing bias currents to particularly low current amplifiers, disrupting amplifier operation.
FIG. 1 is a circuit diagram illustrating a conventional bias circuit for providing bias current to an amplifier.
Referring to FIG. 1, a bias circuit 100 is configured to apply a bias current to a representative low quiescent current amplifier, indicated by transistor 140, such as a Class-B mode or Class-C mode amplifier. As mentioned above, an example of an electronic device having a low quiescent current amplifier is a Doherty amplifier, an example of which is shown in FIG. 2, discussed below.
The bias circuit 100 includes a first resistance 115, a first transistor 120 and a transistor pair 130. The first resistance 115 is connected between an auxiliary bias voltage source (Vaux) and a first node 111, which is also connected to a base of the first transistor 120. The transistor pair 130 includes a second transistor 133 and a third transistor 134 connected in series between the first node 111 and ground. The bias circuit 100 also includes a capacitor 122 connected between the first node 111 and ground.
The first transistor 120 is connected between a supply bias voltage source (Vbias) and a base of the transistor 140 in the low quiescent current amplifier via a second resistance 125. The first transistor 120, the second resistance 125 and the capacitor 122 are thus configured to buffer current supplied to the base of the transistor 140, such that the bias circuit 100 attempts to bias the transistor 140 to a very low quiescent current level. The low quiescent current amplifier also includes an input port 144 (RF IN) connected to the base of the transistor 140, an output port 145 (RF OUT) connected to a collector of the transistor 140, which is also connected to a supply voltage source (Vcc) via a DC feed 147. An emitter of the transistor 140 is connected to ground.
In operation, the first resistance 115 provides the bias current for the second transistor 133 and the third transistor 134 of the transistor pair 130. A reference voltage is generated at the base of the first transistor 120, and is buffered by the first transistor 120 to bias the transistor 140 in the low quiescent current amplifier via the second resistance 125. This topology has two inter-related drawbacks. First, in order to bias the transistor 140 to very low currents (in Class-B mode and Class-C mode) the first resistance 115 must be very large, typically tens or hundreds of kOhms, which is impractical for integration and/or very costly to implement. Second, even with a very large resistance 115, the maximum current into the base of the first transistor 120 and the transistor pair 130 is limited. When the (RF) input signal at the input port 144 is large, the transistor 140 draws significant base current. The first transistor 120 supplies this current by buffering the bias current through the first resistance 115 flowing into its base. However, an increase in current through the first resistance 115 reduces voltage at the base of both the first transistor 120 and the transistor 140. As the input signal continues to increase, there comes a point at which the voltage drops so much that the base current into the transistor 140 cannot be sustained, and thus the output power from the transistor 140 saturates. Accordingly, there is a need for a bias circuit capable of biasing low quiescent current amplifiers to very low current levels (e.g., Class-B mode and Class-C mode).